8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Power Supply Recommendations

The power supply can be any voltage between the min and max supply voltage rating located in Section 5.3.

Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single

supply, TI recommends 0.1 µF and if there are multiple VCC terminals, then TI recommends .01 µF or .022 µF

for each power terminal. It is okay to parallel multiple bypass capacitors to reject different frequencies of noise. A

0.1 µF and 1 µF are commonly used in parallel. The bypass capacitor should be installed as close to the power

terminal as possible for best results.

8.2 Layout

8.2.1 Layout Guidelines

When using multiple bit logic devices inputs should not ever float.

In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two

inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not

be left unconnected because the undefined voltages at the outside connections result in undefined operational

states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital

logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should

be applied to any particular unused input depends on the function of the device. Generally they will be tied to

GND or VCC whichever make more sense or is more convenient. It is generally okay to float outputs unless the

part is a transceiver. If the transceiver has an output enable pin it will disable the outputs section of the part when

asserted. This does not disable the input section of the IOs so they cannot float when disabled.

8.2.2 Layout Example

1

2

3

4

5

6

7

16

15

14

13

12

11

10

GND

VCC

0.1

F

Unused input

tied to GND

Bypass capacitor

placed close to the

device

Avoid 90°

corners for

signal lines

Recommend GND flood fill for

improved signal isolation, noise

reduction, and thermal dissipation

Unused output

left floating

8

9

CLR

1Q

1D

2D

2Q

3D

3Q

GND

VCC

6Q

6D

5D

5Q

4D

4Q

CLK

Figure 8-1. Layout Example for the CDx4ACT174

CD54ACT174, CD74ACT174

SCHS344B – APRIL 2003 – REVISED OCTOBER 2024

www.ti.com

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