P4C187-35JM datasheet(5/12 Pages) PYRAMID

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P4C187/187L

Page 5 of 12

Document # SRAM111 REV B

Notes:

9. CE and WE must be LOW for WRITE cycle.

10. If CE goes HIGH simultaneously with WE HIGH, the output remains

in a high impedance state.

11. Write Cycle Time is measured from the last valid address to the first

transition address.

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE

WE CONTROLLED)(9)

AC CHARACTERISTICS - WRITE CYCLE

CC = 5V ± 10%, All Temperature Ranges)

(2)

Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max

tWC

Write Cycle Time

tCW

Chip Enable Time to

End of Write

12152025303540

tAW

Address Valid to End

of Write

12152025303540

tAS

Address Set-up Time

00000

tWP

Write Pulse Width

tAH

Address Hold Time

from End of Write

00000

tDW

Data Valid to End of

Write

tDH

Data Hold Time00000

00000

tWZ

Write Enable to

Output in High Z

tOW

Output Active from

End of Write

00000

-15-20

-25-35

-45-55

-70-85

Parameter

Symbol

-10

-12

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