P4C1298-35JM datasheet(6/11 Pages) PYRAMID

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P4C1298/L

Page 6 of 11

Document # SRAM135 REV OR

12. Write Cycle Time is measured from the last valid address to the first

transition address.

13. Transition is measured ±200mV from steady state voltage prior to

change with specified loading in Figure 1. This parameter is

sampled and not 100% tested.

Notes:

CE and WE must be LOW for WRITE cycle.

10.

OE is LOW for this WRITE cycle.

11. If

CE goes HIGH simultaneously with WE HIGH, the output remains

in a high impedance state.

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (

WE CONTROLLED) (9)

AC CHARACTERISTICS - WRITE CYCLE

CC = 5V ± 10%, All Temperature Ranges)

(2)

Min

Max

MinMax

tWC

Write Cycle Time

tCW

Chip Enable Time to End of Write

tAW

Address Valid to End of Write

tAS

Address Set-up Time

000

tWP

Write Pulse Width

tAH

Address Hold Time from End of Write

tDW

Data Valid to End of Write

tDH

Data Hold Time

000

tWZ

Write Enable to Output in High Z

tOW

Output Active from End of Write

Sym

Parameter

-45

-15

-20

-25

-35

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