P4C1024L55CWC datasheet(1/11 Pages) PYRAMID

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Document # SRAM125 REV C

Revised September 2006

P4C1024L

LOW POWER 128K x 8

CMOS STATIC RAM

locations are specified on address pins A

0 to A16. Read-

ing is accomplished by device selection (CE

1 low and

CE

2 high) and output enabling (OE) while write enable

(WE) remains HIGH. By presenting the address under

these conditions, the data in the addressed memory lo-

cation is presented on the data input/output pins. The

input/output pins stay in the HIGH Z state when either

CE

1 or OE is HIGH or WE or CE2 is LOW.

The P4C1024L is packaged in a 32-pin TSOP, 445 mil

SOP, and a 600 mil PDIP.

The P4C1024L is a 1,048,576-bit low power CMOS static

RAM organized as 128Kx8. The CMOS memory re-

quires no clocks or refreshing, and has equal access

and cycle times. Inputs are fully TTL-compatible. The

RAM operates from a single 5V±10% tolerance power

supply.

Access times of 55 ns and 70 ns are availale. CMOS is

utilized to reduce power consumption to a low level.

The P4C1024L device provides asynchronous opera-

tion with matching access and cycle times. Memory

Common Data I/O

Three-State Outputs

Fully TTL Compatible Inputs and Outputs

Advanced CMOS Technology

Automatic Power Down

Packages

—32-Pin 600 mil Plastic and Ceramic DIP

—32-Pin 445 mil SOP

—32-Pin TSOP

V

CC Current (Commercial/Industrial)

— Operating: 70mA/85mA

— CMOS Standby: 100µA/100µA

Access Times

—55/70 (Commercial or Industrial)

Single 5 Volts ±10% Power Supply

Easy Memory Expansion Using CE

CE

1, CE2 and OE

OE

Inputs

DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

DIP (P600, C10), SOP (S12)

TOP VIEW

See end of datasheet for TSOP pin configuration.

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Taiwan Memory Technolog...	T15M1024A	85Kb / 13P	128K X 8 LOW POWER CMOS STATIC RAM
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Integrated Circuit Solu...	IS62C1024LL	122Kb / 8P	128K x 8 LOW POWER CMOS STATIC RAM
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