MPC9447

MOTOROLA

TIMING SOLUTIONS

2

GND

Q2

VCC

Q1

GND

Q0

VCC

GND

GND

Q6

VCC

Q7

GND

Q8

VCC

GND

25

26

27

28

29

30

31

32

15

14

13

12

11

10

9

12345678

24

23

22

21

20

19

18

17

16

MPC9447

Figure 1. Logic Diagram

Figure 2. 32--Lead Pinout (Top View)

0

1

CCLK0

CCLK1

CLK_SEL

CLK_STOP

OE

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

CLK

STOP

SYNC

(all input resistors have a value of 25kΩ)

Table 1. Function Table

Control

Default

0

1

CLK_SEL

1

CLK0 input selected

CLK1 input selected

OE

1

Outputs enabled

CLK_STOP

1

Outputs synchronously stopped in logic low state

Outputs active

a. OE = 0 will high--impedance tristate all outputs independent on CLK_STOP

Table 2. Pin Configuration

Pin

I/O

Type

Function

CCLK0

Input

LVCMOS

Clock signal input

CCLK1

Input

LVCMOS

Alternative clock signal input

CLK_SEL

Input

LVCMOS

Clock input select

CLK_STOP

Input

LVCMOS

Clock output enable/disable

OE

Input

LVCMOS

Output enable/disable (high--impedance tristate)

Q0--8

Output

LVCMOS

Clock outputs

GND

Supply

Ground

Negative power supply (GND)

Supply

connected to the positive power supply for correct operation

Table 3. General Specifications

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

Output termination voltage

V

MM

ESD protection (Machine model)

200

V

HBM

ESD protection (Human body model)

2000

V

LU

Latch-up immunity

200

mA

Power dissipation capacitance

10

pF

Per output

Input capacitance

4.0

pF

Inputs

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MPC9447

3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer

NETCOM

IDT™ 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MPC9447

2