P4C116-35JM datasheet(1/14 Pages) PYRAMID

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Document # SRAM110 REV A

Revised October 2005

P4C116/P4C116L

ULTRA HIGH SPEED 2K x 8

STATIC CMOS RAMS

DESCRIPTION

The P4C116/P4C116L are 16,384-bit ultra high-speed

static RAMs organized as 2K x 8. The CMOS memories

require no clocks or refreshing and have equal access

and cycle times. Inputs are fully TTL-compatible. The

RAMs operate from a single 5V±10% tolerance power

supply. Current drain is typically 10 µA from a 2.0V

supply.

Access times as fast as 10 nanoseconds are available,

permitting greatly enhanced system operating speeds.

CMOS is used to reduce power consumption.

The P4C116 is available in 24-pin 300 mil DIP, SOJ and

SOIC packages, a solder seal flatpack and 4 different

LCC packages (24, 28, 32, and 40 pin).

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

FEATURES

Full CMOS, 6T Cell

High Speed (Equal Access and Cycle Times)

– 10/12/15/20/25/35 ns (Commercial)

– 15/20/25/35 ns (Military)

Low Power Operation

Output Enable Control Function

Single 5V±10% Power Supply

Common Data I/O

Fully TTL Compatible Inputs and Outputs

Produced with PACE II TechnologyTM

Standard Pinout (JEDEC Approved)

– 24-Pin 300 mil DIP, SOIC, SOJ

– 24-Pin Solder Seal Flat Pack

– 24-Pin Rectangular LCC (300 x 400 mils)

– 28-Pin Square LCC (450 x 450 mils)

– 32-Pin Rectangular LCC (450 x 550 mils)

– 40-Pin Square LCC (480 x 480 mils)

LCC configurations at end of datasheet

DIP (P4, C4), SOJ (J4), SOIC (S4)

SOLDER SEAL FLAT PACK (FS-1) SIMILAR

Số phần tương tự - P4C116-35JM

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