STAC9750 datasheet(21/73 Pages) IDT

21 / 73 page

STAC9750/9751

VALUE-LINE TWO-CHANNEL AC’97 CODECS

PC AUDIO

IDT™

STAC9750/9751

V 5.8 103106

VALUE-LINE TWO-CHANNEL AC’97 CODECS

5. DIGITAL INTERFACE

5.1.

AC-Link Digital Serial Interface Protocol

The STAC9750/9751 communicates to the AC'97 controller via a 5-wire, digital, serial, AC-Link inter-

face, which is a bi-directional, fixed rate, serial PCM digital stream. All digital audio streams, com-

mands and status information are communicated over this point-to-point serial interconnect. The

AC-Link handles multiple input and output audio streams, as well as control register accesses using

a time division multiplexed (TDM) scheme. The AC'97 controller synchronizes all AC-Link data trans-

action. Table 10 shows the data streams available on the STAC9750/9751:

Synchronization of all AC-Link data transactions is handled by the AC'97 controller. The STAC9750/

9751 drives the serial bit clock onto AC-Link. The AC'97 controller then qualifies with a synchroniza-

tion signal to construct audio frames.

SYNC, fixed at 48 KHz, is derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK, fixed at

12.288 MHz, provides the necessary clocking granularity to support twelve 20-bit outgoing and

incoming time slots. AC-Link serial data is transitioned on each rising edge of BIT_CLK. The receiver

of AC-Link data, STAC9750/9751 for outgoing data and AC'97 controller for incoming data, samples

each serial bit on the falling edges of BIT_CLK.

The AC-Link protocol provides for a special 16-bit (13-bits defined, with 3 Reserved trailing bit posi-

tions) time slot (Slot 0) wherein each bit conveys a “slot-valid” tag for its corresponding time slot

within the current audio frame. A 1 in a given bit position of slot 0 indicates that the corresponding

time slot within the current audio frame has been assigned to a data stream, and contains valid data.

If a slot is tagged invalid, it is the responsibility of the source of the data, (STAC9750/9751 for the

input stream, AC'97 controller for the output stream), to stuff all bit positions with 0s during that slot’s

active time.

SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame. The

portion of the audio frame where SYNC is high is defined as the “Tag Phase”. The remainder of the

audio frame where SYNC is low is defined as the “Data Phase”.

Additionally, for power savings, all clock, SYNC, and data signals can be halted by the controller.

Table 10. STAC9750/9751 Available Data Streams

PCM Playback

2 output slots

2 Channel composite PCM output stream

PCM Record data

2 input slots

2 Channel composite PCM input stream

Control

2 output slots

Control register write port

Status

2 input slots

Control register read port

STAC9750 bảng dữ liệu(PDF) 21 Page - Integrated Device Technology

STAC9750 bảng dữ liệu(HTML) 21 Page - Integrated Device Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

bảng dữ liệu tải về

Link URL