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CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Document #: 38-06059 Rev. *Q
Page 21 of 28
Readback State of Address Counter or Mask Register[42, 43, 44, 45]
Notes:
42. CE0 = OE = BE0 – BE1 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
43. Address in output mode. Host must not be driving address bus after tCKLZ in next clock cycle.
44. Address in input mode. Host can drive address bus after tCKHZ.
45. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.
Switching Waveforms (continued)
CNTEN
CLK
tCH2
tCL2
tCYC2
ADDRESS
ADS
An
Qx-2
Qx-1
Qn
tSA tHA
tSAD tHAD
tSCN tHCN
LOAD
ADDRESS
EXTERNAL
tCD2
INTERNAL
ADDRESS
An+1
An+2
An
tCKHZ
DATAOUT
An*
Qn+3
Qn+1
Qn+2
An+3
An+4
tCKLZ
tCA2 or tCM2
READBACK
INTERNAL
COUNTER
ADDRESS
INCREMENT
EXTERNAL
A0–A16
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