P3C1041 datasheet(1/10 Pages) PYRAMID

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Document # SRAM130 REV OR

Revised October 2005

P3C1041

HIGH SPEED 256K x 16 (4 MEG)

STATIC CMOS RAM

High Speed (Equal Access and Cycle Times)

— 10/12/15/20 ns (Commercial)

— 12/15/20 ns (Industrial)

Low Power

— 325 mW (max.)

Single 3.3V ± 0.3V Power Supply

2.0V Data Retention

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

1519B

FEATURES

DESCRIPTION

The P3C1041 is a 262,144 words by 16 bits high-speed

CMOS static RAM. The CMOS memory requires no

clocks or refreshing, and has equal access and cycle

times. Inputs are fully TTL-compatible. The RAM oper-

ates from a single 3.3V ± 0.3V tolerance power

supply.

Access times as fast as 10 nanoseconds permit greatly

enhanced system operating speeds. CMOS is utilized

to reduce power consumption to a low level. The P3C1041

is a member of a family of PACE RAM™ products offer-

ing fast access times.

The P3C1041 device provides asynchronous operation

with matching access and cycle times. Memory loca-

tions are specified on address pins A

0 to A17. Reading is

accomplished by device selection (CE and output en-

abling (OE) while write enable (WE) remains HIGH. By

presenting the address under these conditions, the data

in the addressed memory location is presented on the

data input/output pins. The input/output pins stay in the

HIGH Z state when either CE or OE is HIGH or WE is

LOW.

Package options for the P3C1041 include 44-pin SOJ

and TSOP packages.

Easy Memory Expansion Using CE

CE

CE and OE

OE

Inputs

Fully TTL Compatible Inputs and Outputs

Advanced CMOS Technology

Fast t

OE

Automatic Power Down when deselected

Packages

—44-Pin SOJ, TSOP II

SOJ

TSOPII

Số phần tương tự - P3C1041

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	P3C1011-10JI	110Kb / 10P	HIGH SPEED 128K x 16 (2 MEG) STATIC CMOS RAM
	P3C1011-10JM	110Kb / 10P	HIGH SPEED 128K x 16 (2 MEG) STATIC CMOS RAM
	P3C1011-10TC	110Kb / 10P	HIGH SPEED 128K x 16 (2 MEG) STATIC CMOS RAM

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