CY7C109D
CY7C1009D
1-Mbit (128K x 8) Static RAM
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-05468 Rev. *E
Revised February 22, 2007
Features
• Pin- and function-compatible with CY7C109B/CY7C1009B
• High speed
—tAA = 10 ns
• Low active power
—ICC = 80 mA @ 10 ns
• Low CMOS standby power
—ISB2 = 3 mA
• 2.0V Data Retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2 and OE options
• CY7C109D available in Pb-free 32-pin 400-Mil wide Molded
SOJ and 32-pin TSOP I packages. CY7C1009D available
in Pb-free 32-pin 300-Mil wide Molded SOJ package
Functional Description [1]
The CY7C109D/CY7C1009D is a high-performance CMOS
static RAM organized as 131,072 words by 8 bits. Easy
memory expansion is provided by an active LOW Chip Enable
(CE1), an active HIGH Chip Enable (CE2), an active LOW
Output Enable (OE), and tri-state drivers.The eight input and
output pins (IO0 through IO7) are placed in a high-impedance
state when:
• Deselected (CE1 HIGH or CE2 LOW),
• Outputs are disabled (OE HIGH),
• When the write operation is active (CE1 LOW, CE2 HIGH,
and WE LOW)
Write to the device by taking Chip Enable One (CE1) and Write
Enable (WE) inputs LOW and Chip Enable Two (CE2) input
HIGH. Data on the eight IO pins (IO0 through IO7) is then
written into the location specified on the address pins (A0
through A16).
Read from the device by taking Chip Enable One (CE1) and
Output Enable (OE) LOW while forcing Write Enable (WE) and
Chip Enable Two (CE2) HIGH. Under these conditions, the
contents of the memory location specified by the address pins
appears on the IO pins.
Logic Block Diagram
IO0
IO7
IO1
IO2
IO3
IO4
IO5
IO6
POWER
DOWN
WE
OE
A0
A1
A2
A3
A4
A5
A6
A7
A8
128K x 8
ARRAY
INPUT BUFFER
CE1
CE2
COLUMN DECODER
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
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