RoboClock®
CY7B9950
Document #: 38-07338 Rev. *C
Page 3 of 10
In addition to determining whether the outputs synchronize to
the rising or the falling edge of the reference signal, the 3-level
PE/HD pin controls the output buffer drive strength as
indicated in Table 6.
The CY7B9950 features split power supply buses for Banks 1
and 2, Bank 3 and Bank 4, which enables the user to obtain
both 3.3V and 2.5V output signals from one device. The core
power supply (VDD) must be set a level that is equal or higher
than on any one of the output power supplies.
Governing Agencies
The following agencies provide specifications that apply to the
CY7B9950. The agency name and relevant specification is
listed below.
Notes:
5. LL disables outputs if TEST = MID and sOE# = HIGH.
6. When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE/HD = HIGH or MID, sOE# disables them LOW when PE/HD = LOW.
7. Please refer to “DC Parameters” section for IOH/IOL specifications.
8. VDDQ1/3/4 must not be set at a level higher than that of VDD. They can be set at different levels from each other, e.g., VDD = 3.3V, VDDQ1 = 3.3V, VDDQ3 = 2.5V
and VDDQ4 = 2.5V.
Table 4. MF Calculation
FS
MF
fNOM at which tU is 1.0 ns(MHz)
L
32
31.25
M16
62.5
H8
125
Table 5. Output Skew Settings
nF[1:0]
Skew (1Q[0:1],2Q[0:1])
Skew (3Q[0:1])
Skew (4Q[0:1])
LL[5]
–4tU
Divide By 2
Divide By 2
LM
–3tU
–6tU
v6tU
LH
–2tU
–4tU
–4tU
ML
–1tU
–2tU
v2tU
MM
Zero Skew
Zero Skew
Zero Skew
MH
+1tU
+2tU
+2tU
HL
+2tU
+4tU
+4tU
HM
+3tU
+6tU
+6tU
HH
+4tU
Divide By 4
Inverted[6]
Table 6. PE/HD Settings
PE/HD
Synchronization
Output Drive Strength[7]
L
Negative
Low Drive
M
Positive
High Drive
H
Positive
Low Drive
Table 7. Power Supply Constraints
VDD
VDDQ1
[8]
VDDQ3
[8]
VDDQ4
[8]
3.3V
3.3V or 2.5V
3.3V or 2.5V
3.3V or 2.5V
2.5V
2.5V
2.5V
2.5V
Table 8.
Agency Name
Specification
JEDEC
JESD 51 (Theta JA)
JESD 65 (Skew, Jitter)
IEEE
1596.3 (Jitter Specs)
UL-194_V0
94 (Moisture Grading)
MIL
883E Method 1012.1 (Therma Theta JC)
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