ADS1626IPAPRG4 datasheet(21/37 Pages) TI

21 / 37 page

ADS1625

ADS1626

SBAS280E − JUNE 2003 − REVISED MAY 2007

www.ti.com

RESETTING THE ADS1625

The ADS1625 and ADS1626 with FIFO disabled are

asynchronously reset when the RESET pin is taken low.

During reset, all of the digital circuits are cleared,

DOUT[17:0] are forced low, and DRDY forced high. It is

recommended that the RESET pin be released on the

falling edge of CLK. Afterwards, DRDY goes low on the

second rising edge of CLK. Allow 46 DRDY cycles for the

digital filter to settle before retrieving data. See Figure 3 for

the timing specifications.

Reset can be used to synchronize multiple ADS1625s. All

devices to be synchronized must use a common CLK

input. With the CLK inputs running, pulse RESET on the

falling edge of CLK, as shown in Figure 15. Afterwards, the

converters will be converting synchronously with the

DRDY

outputs

updating

simultaneously.

After

synchronization, allow 46 DRDY cycles (t12) for output

data to fully settle.

RESET

ADS1625

CLK

DRDY

DOUT[17:0]

DRDY

DOUT[17:0]

RESET

Clock

RESET

ADS1625

CLK

DRDY

DOUT[17:0]

DRDY

DOUT[17:0]

CLK

RESET

DRDY

DOUT[17:0]

Synchronized

Settled

Data

Settled

Data

DRDY

DOUT[17:0]

Figure 15. Synchronizing Multiple Converters

RESETTING THE ADS1626

The ADS1626 with the FIFO enabled requires a different

reset sequence than the ADS1625, as shown in Figure 16.

Ignore any DRDY toggles that occur while RESET is low.

Release RESET on the rising edge of CLK, then

afterwards toggle RD to complete the reset sequence.

Toggle RD to complete reset sequence

CLK

RESET

DRDY

Ignore

Figure 16. Resetting the ADS1626 with the FIFO

Enabled

After resetting, the settling time for the ADS1626 is 46 CLK

cycles, regardless of the FIFO level. Therefore, for higher

FIFO levels, it takes fewer DRDY cycles to settle because

the DRDY period is longer. Table 4 shows the number of

DRDY cycles required to settle for each FIFO level.

Table 4. ADS1626 Reset Settling

FIFO LEVEL

FILTER SETTLING TIME AFTER RESET

(t26 in units of DRDY cycles )

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