ICS83905AMLF datasheet(11/19 Pages) IDT

11 / 19 page

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER

ICS83905AM REV. B JULY 9, 2007

ICS83905

LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER

APPLICATION INFORMATION

CRYSTAL INPUT INTERFACE

Figure 2 shows an example of ICS83905 crystal interface with a

parallel resonant crystal. The frequency accuracy can be fine

tuned by adjusting the C1 and C2 values. For a parallel crystal

with loading capacitance CL = 18pF, we suggest C1 = 15pF and

C2 = 15pF to start with. These values may be slightly fine tuned

further to optimize the frequency accuracy for different board

layouts. Slightly increasing the C1 and C2 values will slightly reduce

the frequency. Slightly decreasing the C1 and C2 values will slightly

increase the frequency. For the oscillator circuit below, R1 can be

used, but is not required. For new designs, it is recommended

that R1 not be used.

FIGURE 2. CRYSTAL OSCILLATOR INTERFACE

15p

R1 (optional)

18pF Parallel Cry stal

15p

XTAL_IN

XTAL_OUT

LVCMOS TO XTAL INTERFACE

The XTAL_IN input can accept a single-ended LVCMOS

signal through an AC couple capacitor. A general interface

diagram is shown in Figure 3. The XTAL_OUT pin can be left

floating. The input edge rate can be as slow as 10ns. For

LVCMOS inputs, it is recommended that the amplitude be

reduced from full swing to half swing in order to prevent signal

interference with the power rail and to reduce noise. This

configuration requires that the output impedance of the driver

(Ro) plus the series resistance (Rs) equals the transmission

line impedance. In addition, matched termination at the crystal

input will attenuate the signal in half. This can be done in one

of two ways. First, R1 and R2 in parallel should equal the

transmission line impedance. For most 50

Ω applications, R1

and R2 can be 100

Ω. This can also be accomplished by

removing R1 and making R2 50

Ω.

FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE

XTAL_IN

XTAL_OUT

VCC

Zo = 50

VCC

.1uf

VDD

Zo = Ro + Rs

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