MPC940LAC datasheet(3/11 Pages) IDT

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MPC940L

LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP

IDT™ / ICS™ 1:18 CLOCK DISTRIBUTION CHIP

MPC940L REV 7 JUNE 5, 2007

Table 2. Absolute Maximum Ratings(1)

1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or

conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is

not implied.

Symbol

Parameter

Min

Max

Unit

VCC

Supply Voltage

–0.3

3.6

Input Voltage

–0.3

VDD + 0.3

IIN

Input Current

±20

TStor

Storage Temperature Range

–40

125

°C

Table 3. DC Characteristics (TA = 0° to 70°C, VCCI = 3.3 V ±5%; VCCO = 3.3 V ±5%)

Symbol

Characteristic

Min

Typ

Max

Unit

Condition

VIH

Input HIGH Voltage

CMOS_CLK

2.4

VCCI

VIL

Input LOW Voltage

CMOS_CLK

0.8

VPP

Peak-to-Peak Input Voltage

PECL_CLK

500

1000

VCMR

Common Mode Range

PECL_CLK

VCCI – 1.4

VCCI – 0.6

VOH

Output HIGH Voltage

2.4

IOH = –20 mA

VOL

Output LOW Voltage

0.5

IOL = 20 mA

IIN

Input Current

±200

µA

CIN

Input Capacitance

4.0

Cpd

Power Dissipation Capacitance

per output

ZOUT

Output Impedance

Ω

ICC

Maximum Quiescent Supply Current

0.5

1.0

Table 4. AC Characteristics (TA = 0° to 70°C, VCCI = 3.3 V ±5%; VCCO = 3.3 V ±5%)

Symbol

Characteristic

Min

Typ

Max

Unit

Condition

Fmax

Maximum Input Frequency

250

MHz

tPLH

Propagation Delay

PECL_CLK

≤ 150 MHz

CMOS_CLK

≤ 150 MHz

2.0

1.8

2.7

2.5

3.4

3.0

tPLH

Propagation Delay

PECL_CLK > 150 MHz

CMOS_CLK > 150 MHz

2.0

1.8

2.9

2.4

3.7

3.2

tsk(o)

Output-to-Output Skew

PECL_CLK

CMOS_CLK

150

tsk(pp)

Part-to-Part Skew

PECL_CLK

≤ 150 MHz

CMOS_CLK

≤ 150 MHz

1.4

1.2

Note (1)

1. Across temperature and voltage ranges. Includes output skew.

tsk(pp)

Part-to-Part Skew

PECL_CLK > 150 MHz

CMOS_CLK > 150 MHz

1.7

1.4

Note (1)

tsk(pp)

Part-to-Part Skew

PECL_CLK

CMOS_CLK

850

750

Note (2)

2. For specific temperature and voltage. Includes output skew.

Output Duty Cycle

fCLK < 134 MHz

fCLK ≤ 250 MHz

Input DC = 50%

tr, tf

Output Rise/Fall Time

0.3

1.1

0.5 – 2.4 V

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