6

ICS97ULP877A

7116—03/27/07

Timing R equirements

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

Max clock frequency

1.8V+0.1V @ 25°C

95

410

MHz

Application Frequency

Range

1.8V+0.1V @ 25°C

160

350

MHz

Input clock duty cycle

40

60

%

CLK stabilization

15

µs

NOTE: The PLL must be able to handle spread spectrum induced skew.

NOTE: Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not

required to meet the other timing parameters. (Used for low speed system debug.)

NOTE: Application clock frequency indicates a range over which the PLL must meet all timing parameters.

NOTE: Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback

signal to its reference signal, within the value specificied by the Static Phase Offset (

normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock

of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode

and later return to active operation. CK and CK may be left floating after they have been driven low for one

complete clock cycle.