AD9627

Preliminary Technical Data

Rev. PrA | Page 4 of 40

SPECIFICATIONS

ADC DC SPECIFICATIONS

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS

enabled, Fast Detect Outputs disabled, Signal Monitor disabled, unless otherwise noted.

Table 1.

AD9627BCPZ-80

AD9627BCPZ-105

AD9627BCPZ-125

AD9627BCPZ-150

Unit

Parameter

Temp

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

RESOLUTION

Full

12

12

12

12

Bits

ACCURACY

No Missing Codes

Full

Guaranteed

Guaranteed

Guaranteed

Guaranteed

Offset Error

Full

±0.3

±TBD

±0.3

±TBD

±0.3

±TBD

±0.3

±TBD

% FSR

Gain Error

Full

±2.0

±2.0

±1.7

±1.7

% FSR

Differential

Full

±TBD

±TBD

±TBD

±TBD

LSB

25°C

±0.4

±0.4

±0.4

±0.4

LSB

Integral Nonlinearity

Full

±TBD

±TBD

±TBD

±TBD

LSB

25°C

±2

±1.8

±2

±2

LSB

TEMPERATURE DRIFT

Offset Error

Full

±15

±15

±15

±15

ppm/°C

Gain Error

Full

±95

±95

±95

±95

ppm/°C

INTERNAL VOLTAGE

REFERENCE

Output Voltage Error

(1 V Mode)

Full

TBD

TBD

TBD

TBD

mV

Load Regulation @ 1.0

mA

Full

TBD

TBD

TBD

TBD

mV

INPUT REFERRED NOISE

VREF = 1.0 V

25°C

TBD

TBD

TBD

TBD

LSB rms

ANALOG INPUT

Input Span, VREF = 1.0

V

Full

2

2

2

2

V p-p

Full

8

8

8

8

pF

VREF INPUT RESISTANCE

Full

6

6

6

6

kΩ

POWER SUPPLIES

Supply Voltage

AVDD, DVDD

Full

1.7

1.8

1.9

1.7

1.8

1.9

1.7

1.8

1.9

1.7

1.8

1.9

V

DRVDD (CMOS

Mode)

Full

1.7

3.3

3.6

1.7

3.3

3.6

1.7

3.3

3.6

1.7

3.3

3.6

V

Supply Current

Full

219

292

363

384

mA

Full

29

37

45

47.5

mA

Full

27

34

42

47.6

mA

Full

TBD

TBD

TBD

TBD

mA

PSRR

Full

±0.01

±0.01

±0.01

±0.01

% FSR

POWER CONSUMPTION

DC Input

Full

TBD

TBD

TBD

TBD

mW

(DRVDD=1.8V)

Full

TBD

TBD

TBD

TBD

mW

(DRVDD=3.3V)

Full

536

705

873

934

mW

Full

TBD

TBD

TBD

TBD

mW

Powerdown Power

Full

TBD

TBD

TBD

TBD

mW