ICS8741004 datasheet(10/17 Pages) IDT

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ICS8741004

DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR

IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR

ICS8741004AG REV. AAUGUST 3, 2007

Differential Clock Input Interface

The CLK /CLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and

other differential signals. Both signals must meet the VPP and

VCMR input requirements. Figures 3A to 3D show interface

examples for the HiPerClockS CLK/CLK input driven by the most

common driver types. The input interfaces suggested here are

examples only. Please consult with the vendor of the driver

component to confirm the driver termination requirements. For

example, in Figure 3A, the input termination applies for IDT

HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver

from another vendor, use their termination recommendation.

Figure 3A. HiPerClockS CLK/CLK Input Driven by an

IDT HiPerClockS LVHSTL Driver

Figure 3C. HiPerClockS CLK/CLK Input

Driven by a 3.3V LVPECL Driver

Figure 3B. HiPerClockS CLK/CLK Input

Driven by a 3.3V LVPECL Driver

Figure 3D. HiPerClockS CLK/CLK Input Driven by

a 3.3V LVDS Driver

1.8V

Zo = 50

Ω

Zo = 50

Ω

CLK

nCLK

3.3V

LVHSTL

IDT

HiPerClockS

LVHSTL Driver

HiPerClockS

Input

125

3.3V

Zo = 50

Ω

Zo = 50

Ω

CLK

nCLK

3.3V

LVPECL

HiPerClockS

Input

CLK

nCLK

HiPerClockS

Input

LVPECL

3.3V

Zo = 50

Ω

Zo = 50

Ω

3.3V

100

LVDS

CLK

nCLK

3.3V

Receiver

Zo = 50

Ω

Zo = 50

Ω

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