CS8420-CS datasheet(90/94 Pages) CIRRUS

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DS245F4

CS8420

16.3.4

Jitter Tolerance

Shown in Figure 43 is the Receiver Jitter Tolerance template as illustrated in the AES3 and IEC60958-4

specification. CS8420 parts used with the appropriate external PLL component values (as noted in

Table 19) have been tested to pass this template.

16.3.5

Jitter Attenuation

Shown in Figure 44 and Figure 45 are jitter attenuation plots for the various revisions of the CS8420 when

used with the appropriate external PLL component values (as noted in Table 19). The AES3 and

IEC60958-4 specifications do not have allowances for locking to sample rates less than 32 kHz or for lock-

ing to the ILRCK input. These specifications state a maximum of 2 dB jitter gain or peaking.

Figure 43. Jitter Tolerance Template

−1

−20

−15

−10

−5

Jitter Frequency (Hz)

−1

−25

−20

−15

−10

−5

Jitter Frequency (Hz)

Figure 44. Revision D Jitter Attenuation

Figure 45. Revision D1 Jitter Attenuation

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