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UAA3545 bảng dữ liệu(PDF) 18 Page - NXP Semiconductors |
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UAA3545 bảng dữ liệu(HTML) 18 Page - NXP Semiconductors |
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18 / 28 page ![]() This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... FCA246 UAA3545 1 2 3 4 5 6 7 8 RFB TXB TXA RFA 9 101112 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 R11 2.2 k Ω C18 8.2 nF NPO C13 560 pF NPO C22 82 pF C57 100 nF C58 10 µF VCC S_DATA(1) S_EN R_DATAP S_CLK XTAL C31 1 nF C40 4.7 nF SLCCTR RSSI C44 27 pF C46 8.2 pF VCC L8 6.8 nH C41 8.2 pF C40 8.2 pF L10 6.8 nH L9 6.8 nH C43 1.5 pF C42 1.5 pF RF input C33 0.82 pF C27 0.82 pF TX output C28 8.2 pF C32 8.2 pF L6 2.7 nH(2) L5 2.7 nH L4 12 nH L7 12 nH C70 8.2 pF C62 1.8 pF C68 8.2 pF VCC C69 8.2 pF C23 100 nF C67 6.8 pF C65 6.8 pF C66 100 nF T_GFSK VCO_ON R 470 Ω C 8.2pF R 470 Ω C 8.2 pF PA T_PWR ADDITIONAL IMPLEMENTATION Fig.6 Evaluation board schematic (mode 3 operation). (1) S_DATA input (pin 4) is subject to latch-up if a negative voltage is applied. The application circuit should be designed to prevent this occurring. (2) TXA and TXB outputs (pins 20 and 21) are subject to latch-up if a negative output voltage occurs. To prevent this happening, the application circuit should use a DC biasing arrangement with L5 and L6 connected to VCC as shown. |
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