PIC24HJ12GP201ESLASHML datasheet(174/234 Pages) MICROCHIP

174 / 234 page

PIC24HJ12GP201/202

DS70282B-page 172

Preliminary

All instructions are a single word, except for certain

double-word instructions, which were made double-

word instructions so that all the required information is

available in these 48 bits. In the second word, the

8MSbs are ‘0’s. If this second word is executed as an

instruction (by itself), it will execute as a NOP.

Most single-word instructions are executed in a single

instruction cycle, unless a conditional test is true, or the

program counter is changed as a result of the instruc-

tion. In these cases, the execution takes two instruction

cycles with the additional instruction cycle(s) executed

as a NOP. Notable exceptions are the BRA (uncondi-

tional/computed branch), indirect CALL/GOTO, all table

reads and writes and RETURN/RETFIE instructions,

which are single-word instructions but take two or three

cycles. Certain instructions that involve skipping over the

subsequent instruction require either two or three cycles

if the skip is performed, depending on whether the

instruction being skipped is a single-word or double-

word instruction. Moreover, double-word moves require

two cycles. The double-word instructions execute in two

instruction cycles.

Note:

For more details on the instruction set,

refer to the “dsPIC30F/33F Programmer’s

Reference Manual” (DS70157).

TABLE 19-1:

SYMBOLS USED IN OPCODE DESCRIPTIONS

Field

Description

#text

Means literal defined by “text”

(text)

Means “content of text”

[text]

Means “the location addressed by text”

{ }

Optional field or operation

<n:m>

Byte mode selection

Double Word mode selection

Shadow register select

Word mode selection (default)

bit4

4-bit bit selection field (used in word addressed instructions)

∈ {0...15}

C, DC, N, OV, Z

MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero

Expr

Absolute address, label or expression (resolved by the linker)

File register address

∈ {0x0000...0x1FFF}

lit1

1-bit unsigned literal

∈ {0,1}

lit4

4-bit unsigned literal

∈ {0...15}

lit5

5-bit unsigned literal

∈ {0...31}

lit8

8-bit unsigned literal

∈ {0...255}

lit10

10-bit unsigned literal

∈ {0...255} for Byte mode, {0:1023} for Word mode

lit14

14-bit unsigned literal

∈ {0...16384}

lit16

16-bit unsigned literal

∈ {0...65535}

lit23

23-bit unsigned literal

∈ {0...8388608}; LSB must be ‘0’

None

Field does not require an entry, may be blank

Program Counter

Slit10

10-bit signed literal

∈ {-512...511}

Slit16

16-bit signed literal

∈ {-32768...32767}

Slit6

6-bit signed literal

∈ {-16...16}

Base W register

∈ {W0..W15}

Destination W register

∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }

Wdo

Destination W register

∈

{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }

Wm,Wn

Dividend, Divisor working register pair (direct addressing)

Wm*Wm

Multiplicand and Multiplier working register pair for Square instructions

∈

{W4 * W4,W5 * W5,W6 * W6,W7 * W7}

Wm*Wn

Multiplicand and Multiplier working register pair for DSP instructions

∈

{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}

One of 16 working registers

∈ {W0..W15}

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