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PIC18F4685-I/SP bảng dữ liệu(PDF) 38 Page - Microchip Technology

tên linh kiện PIC18F4685-I/SP
Giải thích chi tiết về linh kiện  28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
PDF  484 Pages
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nhà sản xuất  MICROCHIP [Microchip Technology]
Trang chủ  http://www.microchip.com
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PIC18F4685-I/SP bảng dữ liệu(HTML) 38 Page - Microchip Technology

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PIC18F2682/2685/4682/4685
DS39761B-page 36
Preliminary
© 2007 Microchip Technology Inc.
If the IRCF bits were previously at a non-zero value or
if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, the IOFS bit will
remain set.
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
primary clock becomes ready, a clock switch to the
primary clock occurs (see Figure 3-4). When the clock
switch is complete, the IOFS bit is cleared, the OSTS
bit is set and the primary clock is providing the device
clock. The IDLEN and SCS bits are not affected by the
switch. The INTRC source will continue to run if either
the WDT or the Fail-Safe Clock Monitor is enabled.
FIGURE 3-3:
TRANSITION TIMING TO RC_RUN MODE
FIGURE 3-4:
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q4
Q3
Q2
OSC1
Peripheral
Program
Q1
INTRC
Q1
Counter
Clock
CPU
Clock
PC + 2
PC
123
n-1
n
Clock Transition
Q4
Q3
Q2
Q1
Q3
Q2
PC + 4
Q1
Q3 Q4
OSC1
Peripheral
Program
PC
INTOSC
PLL Clock
Q1
PC + 4
Q2
Output
Q3
Q4
Q1
CPU Clock
PC + 2
Clock
Counter
Q2
Q2
Q3
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
SCS1:SCS0 bits Changed
TPLL(1)
12
n-1
n
Clock
OSTS bit Set
Transition
Multiplexer
TOST(1)



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