PIC18F4685-ISLASHSP datasheet(201/484 Pages) MICROCHIP

201 / 484 page

Preliminary

DS39761B-page 199

PIC18F2682/2685/4682/4685

SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MODE)

R/W-0

GCEN

ACKSTAT

ACKDT(1)

ACKEN(2)

RCEN(2)

PEN(2)

RSEN(2)

SEN(2)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

GCEN: General Call Enable bit (Slave mode only)

= Enable interrupt when a general call address (0000h) is received in the SSPSR

= General call address disabled

bit 6

ACKSTAT: Acknowledge Status bit (Master Transmit mode only)

= Acknowledge was not received from slave

= Acknowledge was received from slave

bit 5

ACKDT: Acknowledge Data bit (Master Receive mode only)(1)

= Not Acknowledge

= Acknowledge

bit 4

ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)(2)

= Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically

cleared by hardware.

= Acknowledge sequence Idle

bit 3

RCEN: Receive Enable bit (Master mode only)(2)

= Enables Receive mode for I2C

= Receive Idle

bit 2

PEN: Stop Condition Enable bit (Master mode only)(2)

= Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.

= Stop condition Idle

bit 1

RSEN: Repeated Start Condition Enable bit (Master mode only(2)

= Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.

= Repeated Start condition Idle

bit 0

SEN: Start Condition Enable/Stretch Enable bit(2)

In Master mode:

= Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.

= Start condition Idle

In Slave mode:

= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)

= Clock stretching is disabled

Note 1:

Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.

For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, these bits may not be

set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).

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