PIC18F44J10-ESLASHP datasheet(33/358 Pages) MICROCHIP

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Preliminary

DS39682C-page 31

PIC18F45J10 FAMILY

3.0

POWER-MANAGED MODES

The PIC18F45J10 family devices provide the ability to

manage power consumption by simply managing clock-

ing to the CPU and the peripherals. In general, a lower

clock frequency and a reduction in the number of circuits

being clocked constitutes lower consumed power. For

the sake of managing power in an application, there are

three primary modes of operation:

• Run mode

• Idle mode

• Sleep mode

These modes define which portions of the device are

clocked and at what speed. The Run and Idle modes

may use any of the three available clock sources

(primary, secondary or internal oscillator block); the

Sleep mode does not use a clock source.

The

power-managed

modes

include

several

power-saving features offered on previous PIC®

devices. One is the clock switching feature, offered in

other PIC18 devices, allowing the controller to use the

Timer1 oscillator in place of the primary oscillator. Also

included is the Sleep mode, offered by all PIC devices,

where all device clocks are stopped.

3.1

Selecting Power-Managed Modes

Selecting a power-managed mode requires two

decisions: if the CPU is to be clocked or not and which

clock

source

used.

The

IDLEN

bit

(OSCCON<7>) controls CPU clocking, while the

SCS1:SCS0 bits (OSCCON<1:0>) select the clock

source. The individual modes, bit settings, clock

sources and affected modules are summarized in

Table 3-1.

3.1.1

CLOCK SOURCES

The SCS1:SCS0 bits allow the selection of one of three

clock sources for power-managed modes. They are:

• the primary clock, as defined by the

FOSC1:FOSC0 configuration bits

• the secondary clock (Timer1 oscillator)

• the internal oscillator

3.1.2

ENTERING POWER-MANAGED

MODES

Switching from one power-managed mode to another

begins

the

OSCCON

The

SCS1:SCS0 bits select the clock source and determine

which Run or Idle mode is to be used. Changing these

bits causes an immediate switch to the new clock

source, assuming that it is running. The switch may

also be subject to clock transition delays. These are

discussed in Section 3.1.3 “Clock Transitions and

Status Indicators” and subsequent sections.

Entry to the power-managed Idle or Sleep modes is

triggered by the execution of a SLEEP instruction. The

actual mode that results depends on the status of the

IDLEN bit.

Depending on the current mode and the mode being

switched to, a change to a power-managed mode does

not always require setting all of these bits. Many

transitions may be done by changing the oscillator

select bits, or changing the IDLEN bit, prior to issuing a

SLEEP

instruction. If the IDLEN bit is already

configured correctly, it may only be necessary to

perform a SLEEP instruction to switch to the desired

mode.

TABLE 3-1:

POWER-MANAGED MODES

Mode

OSCCON bits

Module Clocking

Available Clock and Oscillator Source

IDLEN<7>(1) SCS1:SCS0<1:0>

CPU

Peripherals

Sleep

N/A

Off

None – All clocks are disabled

PRI_RUN

N/A

Clocked

Primary – HS, EC;

this is the normal full power execution mode

SEC_RUN

N/A

Clocked

Secondary – Timer1 Oscillator

RC_RUN

N/A

Clocked

Internal Oscillator

PRI_IDLE

110

Off

Clocked

Primary – HS, EC

SEC_IDLE

101

Off

Clocked

Secondary – Timer1 Oscillator

RC_IDLE

111

Off

Clocked

Internal Oscillator

Note 1:

IDLEN reflects its value when the SLEEP instruction is executed.

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