C8051F062 datasheet(52/328 Pages) SILABS

52 / 328 page

C8051F060/1/2/3/4/5/6/7

Rev. 1.2

Figure 5.2. 16-bit ADC0 and ADC1 Data Path Diagram

5.1.

Single-Ended or Differential Operation

ADC0 and ADC1 can be programmed to operate independently as single-ended ADCs, or together to

accept a differential input. In single-ended mode, the ADCs can be configured to sample simultaneously, or

to use different conversion speeds. In differential mode, ADC1 is a slave to ADC0, and its configuration is

based on ADC0 settings, except during offset or gain calibrations. The DIFFSEL bit in the Channel Select

5.1.1. Pseudo-Differential Inputs

The inputs to the ADCs are pseudo-differential. The actual voltage measured by each ADC is equal to the

voltage between the AINn pin and the AINnG pin. AINnG must be a DC signal between -0.2 and 0.6 V. In

most systems, AINnG will be connected to AGND. If not tied to AGND, the AINnG signal can be used to

negate a limited amount of fixed offset, but it is recommended that the internal offset calibration features of

the device be used for this purpose. When operating in differential mode, AIN0G and AIN1G should be tied

together. AINn must remain above AINnG in both modes for accurate conversion results.

AIN0

16-Bit

SAR

ADC0

AMX0SL

AIN1

16-Bit

SAR

ADC1

ADC0H

ADC0L

ADC1H

ADC1L

Single-Ended

Differential

ADC0LTL

ADC0LTH

ADC0GTL

ADC0GTH

AD0WINT

Window

Compare

DMA

Interface

AIN0G

AIN1G

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