ENC28J60-CSLASHSS datasheet(29/96 Pages) MICROCHIP

29 / 96 page

Preliminary

DS39662B-page 27

ENC28J60

4.2.1

READ CONTROL REGISTER

COMMAND

The Read Control Register (RCR) command allows the

host controller to read any of the ETH, MAC and MII

registers in any order. The contents of the PHY regis-

ters are read via a special MII register interface (see

Section 3.3.1 “Reading PHY Registers” for more

information).

The RCR command is started by pulling the CS pin low.

The RCR opcode is then sent to the ENC28J60,

followed by a 5-bit register address (A4 through A0).

The 5-bit address identifies any of the 32 control

registers in the current bank. If the 5-bit address is an

ETH register, then data in the selected register will

immediately start shifting out MSb first on the SO pin.

Figure 4-3 shows the read sequence for these

registers.

If the address specifies one of the MAC or MII registers,

a dummy byte will first be shifted out the SO pin. After

the dummy byte, the data will be shifted out MSb first

on the SO pin. The RCR operation is terminated by

raising the CS pin. Figure 4-4 shows the read

sequence for MAC and MII registers.

FIGURE 4-3:

READ CONTROL REGISTER COMMAND SEQUENCE (ETH REGISTERS)

FIGURE 4-4:

READ CONTROL REGISTER COMMAND SEQUENCE

(MAC AND MII REGISTERS)

SCK

234

567

Data Out

Opcode

Address

High-Impedance State

SCK

234567

10 11 12 13 14 15 16 17 18 19 20 21 22

765432

Opcode

Dummy Byte

High-Impedance State

6543210

Data Byte Out

Address

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