M58LT128HST datasheet(12/110 Pages) STMICROELECTRONICS

12 / 110 page

Signal descriptions

M58LT128HST, M58LT128HSB

12/110

Signal descriptions

See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals

connected to this device.

2.1

Address inputs (A0-A22)

The Address Inputs select the cells in the memory array to access during Bus Read

operations. During Bus Write operations they control the commands sent to the Command

Interface of the Program/Erase Controller.

2.2

Data inputs/outputs (DQ0-DQ15)

The Data I/O output the data stored at the selected address during a Bus Read operation or

input a command or the data to be programmed during a Bus Write operation.

2.3

Chip Enable (E)

The Chip Enable input activates the memory control logic, input buffers, decoders and

sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active

mode. When Chip Enable is at VIH the memory is deselected, the outputs are high

impedance and the power consumption is reduced to the standby level.

2.4

Output Enable (G)

The Output Enable input controls data outputs during the Bus Read operation of the

memory.

2.5

Write Enable (W)

The Write Enable input controls the Bus Write operation of the memory’s Command

Interface. The data and address inputs are latched on the rising edge of Chip Enable or

Write Enable whichever occurs first.

2.6

Reset (RP)

The Reset input provides a hardware reset of the memory. When Reset is at VIL, the

memory is in reset mode: the outputs are high impedance and the current consumption is

reduced to the Reset Supply Current IDD2. Refer to Table 20: DC characteristics - currents,

for the value of IDD2. After Reset all blocks are in the Protected state and the Configuration

mode the device enters asynchronous read mode, but a negative transition of Chip Enable

or Latch Enable is required to ensure valid data outputs.

M58LT128HST bảng dữ liệu(PDF) 12 Page - STMicroelectronics