IDT74FST3257SO datasheet(4/5 Pages) IDT

4 / 5 page

10.3

IDT74FST3257

QUAD 2:1 MUX/DEMUX BUS SWITCH

COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS

TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION

PROPAGATION DELAY

ENABLE AND DISABLE TIMES

PULSE WIDTH

SET-UP, HOLD AND RELEASE TIMES

Test

Switch

Disable Low

Enable Low

Closed

All Other Tests

Open

Open Drain

DEFINITIONS:

CL=

Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse

Generator.

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable-

HIGH

2. Pulse Generator for All Pulses: Rate

≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns

Pulse

Generator

R T

D.U.T.

V CC

VIN

C L

VOUT

50pF

500

Ω

500

Ω

7.0V

1.5V

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

tSU

tREM

tSU

HIGH-LOW-HIGH

PULSE

LOW-HIGH-LOW

PULSE

1.5V

SAME PHASE

INPUT TRANSITION

1.5V

VOH

tPLH

OUTPUT

OPPOSITE PHASE

INPUT TRANSITION

1.5V

tPLH

tPHL

VOL

CONTROL

INPUT

1.5V

3.5V

OUTPUT

NORMALLY

LOW

OUTPUT

NORMALLY

HIGH

SWITCH

CLOSED

SWITCH

OPEN

VOL

0.3V

tPLZ

tPZL

tPZH

tPHZ

3.5V

1.5V

ENABLE

DISABLE

VOH

PRESET

CLEAR

CLOCK ENABLE

ETC.

3257 lnk 08

3257 lnk 03

3257 lnk 04

3257 lnk 03

3257 lnk 06

3257 lnk 07

IDT74FST3257SO bảng dữ liệu(PDF) 4 Page - Integrated Device Technology

IDT74FST3257SO bảng dữ liệu(HTML) 4 Page - Integrated Device Technology

Html Pages

1 2 3 4 5

bảng dữ liệu tải về

Link URL