93LC86AT-ESLASHMS datasheet(15/38 Pages) MICROCHIP

15 / 38 page

DS21929D-page 15

93XX46X/56X/66X/76X/86X

3.8

WRITE

The WRITE instruction is followed by 8 bits (If ORG is

low or A-version devices) or 16 bits (If ORG pin is high

or B-version devices) of data which are written into the

specified address. For 93AAXX and 93LCXX devices,

after the last data bit is clocked into DI, the falling edge

of CS initiates the self-timed auto-erase and program-

ming cycle. For 93CXX devices, the self-timed auto-

erase and programming cycle is initiated by the rising

edge of CLK on the last data bit.

The DO pin indicates the Ready/Busy status of the

device, if CS is brought high after a minimum of 250 ns

low (TCSL). DO at logical ‘0’ indicates that programming

is still in progress. DO at logical ‘1’ indicates that the

the data specified and the device is ready for another

instruction.

FIGURE 3-8:

WRITE TIMING FOR 93AAXX AND 93LCXX DEVICES

FIGURE 3-9:

WRITE TIMING FOR 93CXX DEVICES

Note:

For devices with PE functionality such as

the 93XX76C or 93XX86C, the write

sequence requires a logic high signal on

the PE pin prior to the rising edge of clock

on the last data bit.

Note:

After the Write cycle is complete, issuing a

Start bit and then taking CS low will clear

the Ready/Busy status from DO.

CLK

•••

Busy

Ready

High-Z

Twc

TCSL

TCZ

TSV

CLK

•••

Busy

Ready

High-Z

Twc

TCSL

TCZ

TSV

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