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ZY7015HT2 bảng dữ liệu(PDF) 21 Page - Power-One

tên linh kiện ZY7015HT2
Giải thích chi tiết về linh kiện  3V to 13.2V Input 0.5V to 5.5V Output
PDF  34 Pages
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nhà sản xuất  POWER-ONE [Power-One]
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ZY7015HT2 bảng dữ liệu(HTML) 21 Page - Power-One

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ZY7015 15A DC-DC Intelligent POL Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
LR2
LR
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
R/W-1
R/W-1
1
LR0
TCE
CLS2
CLS1
CLS0
Bit 7
Bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
Bit 7:5 LR[2:0], Load regulation configuration
000: 0 V/A/Ohm
001: 0.39 V/A/Ohm
010: 0.78 V/A/Ohm
011: 1.18 V/A/Ohm
100: 1.57 V/A/Ohm
101: 1.96 V/A/Ohm
110: 2.35 V/A/Ohm
111: 2.75 V/A/Ohm
Bit 4
TCE, Temperature compensation enable
0: disabled
1: enabled
Bit 3:0 CLS[3:0], Current limit setting
0h: corresponds to 37%
1h: corresponds to 47%
…
Bh: corresponds to 140%
Values higher than Bh are translated to Bh (140%)
CLS3
Figure 38. Current Limit Setpoint Register CLS
---
---
---
PGLL
OVPL0
UVPL1
UVPL0
Bit 7
Bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
U
U
U
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
Bit 7:5 Unimplemented, read as ‘0’
Bit 4
PGLL: Set Power Good Low Level
1 = 95% of Vo
0 = 90% of Vo (Default)
Bit 3:2 OVPL[1:0]: Set Over Voltage Protection
Level
00 = 110% of Vo
01 = 120% of Vo
10 = 130% of Vo (Default)
11 = 130% of Vo
Bit 1:0 UVPL[1:0]: Set Under Voltage Protection Level
00 = 75% of Vo (Default)
01 = 80% of Vo
10 = 85% of Vo
OVPL1
Figure 39. Protection Configuration Register PC2
Note
tage
rotection thresholds and Power Good limits are
atching
or
non-latching)
or
disable
certain
that
the
overvoltage
and
undervol
p
defined as percentages of the output voltage.
Therefore, the absolute levels of the thresholds
change when the output voltage setpoint is changed
either by output voltage adjustment or by margining.
In addition, a user can change type of protections
(l
protections. These settings are programmed in the
GUI Fault Management window shown in Figure 40
or directly via the I
2C by writing into the PC1 register
shown in Figure 41.
Figure 40. Fault Management Window
Figure 41. Protection Configuration Register PC1
If the non-latching protection is selected, a POL will
attempt to restart every 130ms until the condition
that triggered the protection is removed.
When
restarting, the output voltages follow tracking and
sequencing settings.
If the latching type is selected, a POL will turn off and
stay off. The POL can be turned on after 130ms, if
the condition that caused the fault is removed and
the respective bit in the ST register was cleared, or
the Turn On command was recycled, or the input
voltage was recycled.
TRE
PVE
TRP
OTP
UVP
OVP
PVP
Bit 7
Bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
Bit 7
TRE: Tracking fault enable
1 = enabled
0 = disabled
Bit 6
PVE: Phase voltage error enable
1 = enabled
0 = disabled
Bit 5
TRP: Tracking fault protection
1 = latching
0 = non latching
Bit 4
OTP: Overtemperature protection configuration
1 = latching
0 = non latching
Bit 3
OCP: Overcurrent protection configuration
1 = latching
0 = non latching
Bit 2
UVP: Undervoltage protection configuration
1 = latching
0 = non latching
Bit 1
OVP: Overvoltage protection configuration
1 = latching
0 = non latching
Bit 0
PVP: Phase Voltage Protection
1 = latching
0 = non latching
OCP
ZD-00283 REV. 2.2
www.power-one.com
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