DS2155 datasheet(45/238 Pages) DALLAS

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DS2155

45 of 238

8. CLOCK MAP

Figure 8-1 shows the clock map of the DS2155. The routing for the transmit and receive clocks are shown

for the various loopback modes and jitter attenuator positions. Although there is only one jitter attenuator,

which can be placed in the receive or transmit path, two are shown for simplification and clarity.

Figure 8-1. Clock Map

The TCLK MUX is dependent on the state of the TCSS0 and TCSS1 bits in the CCR1 register and the

state of the TCLK pin.

TCSS1

TCSS0

Transmit Clock Source

The TCLK pin (C) is always the source of transmit clock.

Switch to the recovered clock (B) when the signal at the TCLK pin

fails to transition after one channel time.

Use the scaled signal (A) derived from MCLK as the transmit clock.

The TCLK pin is ignored.

Use the recovered clock (B) as the transmit clock. The TCLK pin is

ignored.

TRANSMIT

FORMATTER

RECEIVE

FRAMER

BPCLK

SYNTH

REMOTE

LOOPBACK

FRAMER

LOOPBACK

PAYLOAD

LOOPBACK

(SEE NOTES)

LTCA

JITTER ATTENUATOR

SEE LIC1 REGISTER

LOCAL

LOOPBACK

BPCLK

RCLK

TCLK

MCLK

RXCLK

TXCLK

LIU

LLB = 0

LLB = 1

PLB = 0

PLB = 1

RLB = 1

RLB = 0

FLB = 1

FLB = 0

JAS = 0

AND

DJA = 0

JAS = 1

DJA = 1

JAS = 0

DJA = 1

JAS = 1

AND

DJA = 0

RCL = 1

RCL = 0

DJA = 1

DJA = 0

8XCLK

8 x PLL

PRE-SCALER

LIC4.MPS0

LIC4.MPS1

LIC2.3

2.048 TO 1.544

SYNTHESIZER

MCLKS = 0

TSYSCLK

MCLKS = 1

TCLK

MUX

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