TDA8752 datasheet(26/36 Pages) PHILIPS

26 / 36 page

1999 Mar 09

Philips Semiconductors

Product speciﬁcation

Triple high speed Analog-to-Digital

Converter (ADC)

TDA8752

Data timing (see Fig.11); fCLK = 100 MHz; CL = 10 pF; note 2

td(s)

sampling delay time

referenced to CKADCO

−−

−

td(o)

output delay time

−−3.3

−2.6

th(o)

output hold time

4.6

5.5

−

3-state output delay time; (see Fig.12)

tdZH

output enable HIGH

−

tdZL

output enable LOW

−

tdHZ

output disable HIGH

−

tdLZ

output disable LOW

−

PLL clock output

VOL

LOW-level output voltage

Io =1mA

−

0.3

0.8

VOH

HIGH-level output voltage

Io = − 1 mA

2.4

3.5

−

IOL

LOW-level output current

VOL = 0.4 V

−

IOH

HIGH-level output current

VOH = 2.7 V

−−0.4

−

ADC data outputs

VOL

LOW-level output voltage

Io =1mA

−

0.8

VOH

HIGH-level output voltage

Io = − 1 mA

2.4

VCCD

−

IOL

LOW-level output current

VOL = 0.4 V

−

IOH

HIGH-level output current

VOH = 2.7 V

−−0.5

−

TTL digital inputs (CKREF, COAST, CKEXT, INV, HSYNC and CLP)

VIL

LOW level input voltage

−−

0.8

VIH

HIGH level input voltage

2.0

−−

IIL

LOW level input current

VIL = 0.4 V

400

−−

µA

IIH

HIGH level input current

VIH = 2.7 V

−−

100

µA

input impedance

−

Ω

input capacitance

−

4.5

−

3-wire serial bus

treset

reset time of the chip before

3-wire communication

−

600

−

tsu

data set-up time

−

100

−

data hold time

−

100

−

I2C-bus; see note 3

fSCL

clock frequency

−

100

kHz

tBUF

time the bus must be free

before new transmission can

start

4.7

−−

µs

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

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