STK15C68 datasheet(8/10 Pages) SIMTEK

8 / 10 page

STK15C68

March 2006

Document Control # ML0009 rev 0.2

Internally, RECALL is a two-step procedure. First,

the SRAM data is cleared, and second, the nonvola-

tile information is transferred into the SRAM cells.

After the t

RECALL cycle time the SRAM will once again

be ready for READ and WRITE operations. The

RECALL

operation in no way alters the data in the

Nonvolatile Elements. The nonvolatile data can be

recalled an unlimited number of times.

AutoStore™ OPERATION

The STK15C68 uses the intrinsic system capaci-

tance to perform an automatic store on power

down. As long as the system power supply takes at

least t

STORE to decay from VSWITCH down to 3.6V, the

STK15C68 will safely and automatically store the

SRAM

data in Nonvolatile Elements on power

down.

In order to prevent unneeded STORE operations,

automatic STORE will be ignored unless at least

one WRITE operation has taken place since the

most recent STORE or RECALL cycle. Software-

initiated STORE cycles are performed regardless of

whether a WRITE operation has taken place.

POWER-UP RECALL

During power up, or after any low-power condition

CC < VRESET), an internal RECALL request will be

latched. When V

CC once again exceeds the sense

voltage of V

SWITCH, a RECALL cycle will automatically

be initiated and will take t

RESTORE to complete.

If the STK15C68 is in a WRITE state at the end of

power-up RECALL, the SRAM data will be corrupted.

To help avoid this situation, a 10K Ohm resistor

should be connected either between W and system

CC or between E and system VCC.

HARDWARE PROTECT

The STK15C68 offers hardware protection against

inadvertent STORE operation and SRAM WRITEs

during low-voltage conditions. When V

CC < VSWITCH,

software STORE operations and SRAM WRITEs are

inhibited.

LOW AVERAGE ACTIVE POWER

The STK15C68 draws significantly less current

when it is cycled at times longer than 50ns. Figure 2

shows the relationship between I

CC and READ cycle

time. Worst-case current consumption is shown for

both CMOS and TTL input levels (commercial tem-

perature range, V

CC= 5.5V, 100% duty cycle on chip

enable). Figure 3 shows the same relationship for

WRITE

cycles. If the chip enable duty cycle is less

than 100%, only standby current is drawn when the

chip is disabled. The overall average current drawn

by the STK15C68 depends on the following items:

1) CMOS vs. TTL input levels; 2) the duty cycle of

chip enable; 3) the overall cycle rate for accesses;

4) the ratio of READs to WRITEs; 5) the operating

temperature; 6) the V

CC level; and 7) I/O loading.

Figure 2: ICC (max) Reads

100

150

200

Cycle Time (ns)

TTL

CMOS

Figure 3: ICC (max) Writes

100

150

200

Cycle Time (ns)

TTL

CMOS

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