93LC76A-ESLASHMS datasheet(7/28 Pages) MICROCHIP

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Giải thích chi tiết về linh kiện	8K Microwire Compatible Serial EEPROM

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DS21796H-page 7

93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C

2.5

Erase All (ERAL)

The Erase All (ERAL) instruction will erase the entire

memory array to the logical ‘1’ state. The ERAL cycle

is identical to the erase cycle, except for the different

opcode. The ERAL cycle is completely self-timed. The

rising edge of CLK before the last data bit initiates the

write cycle. Clocking of the CLK pin is not necessary

after the device has entered the ERAL cycle.

The DO pin indicates the Ready/Busy status of the

device, if CS is brought high after a minimum of 250 ns

low (TCSL).

VCC must be

≥ 4.5V for proper operation of ERAL.

FIGURE 2-2:

ERAL TIMING

Note:

After the ERAL command is complete,

issuing a Start bit and then taking CS low

will clear the Ready/Busy status from DO.

CLK

TCSL

Check Status

•••

TSV

TCZ

Busy

Ready

High-Z

TEC

High-Z

93LC76A-E/MS bảng dữ liệu(PDF) 7 Page - Microchip Technology