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24FC1025-E/P bảng dữ liệu(PDF) 4 Page - Microchip Technology |
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24FC1025-E/P bảng dữ liệu(HTML) 4 Page - Microchip Technology |
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4 / 22 page ![]() 24AA1025/24LC1025/24FC1025 DS21941E-page 4 Preliminary © 2007 Microchip Technology Inc. FIGURE 1-1: BUS TIMING DATA 17 TWC Write cycle time (byte or page) — 5 ms 3 ms, typical 18 Endurance 1 M — cycles 25°C (Note 4) AC CHARACTERISTICS (Continued) Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to +125°C Param. No. Sym. Characteristic Min. Max. Units Conditions Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but established by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com. 5: Max. clock frequency is 100 kHz for E-temp devices <4.5V. 1.7-2.5V (100 kHz) timings must be used. (unprotected) (protected) SCL SDA IN SDA OUT WP 5 7 6 16 3 2 89 13 D4 4 10 11 12 14 |
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