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MCP3021 bảng dữ liệu(PDF) 4 Page - Microchip Technology |
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MCP3021 bảng dữ liệu(HTML) 4 Page - Microchip Technology |
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4 / 26 page  MCP3021 DS21805A-page 4 2003 Microchip Technology Inc. TIMING SPECIFICATIONS FIGURE 1-1: Standard and Fast Mode Bus Timing Data. Electrical Characteristics: All parameters apply at VDD = 2.7V - 5.5V, VSS = GND, TA = -40°C to +85°C. Parameters Sym Min Typ Max Units Conditions I2C Standard Mode Clock frequency fSCL 0— 100 kHz Clock high time THIGH 4000 — — ns Clock low time TLOW 4700 — — ns SDA and SCL rise time TR — — 1000 ns From VIL to VIH (Note 1) SDA and SCL fall time TF —— 300 ns From VIL to VIH (Note 1) START condition hold time THD:STA 4000 — — ns START condition setup time TSU:STA 4700 — — ns Data input setup time TSU:DAT 250 — — ns STOP condition setup time TSU:STO 4000 — — ns STOP condition hold time THD:STD 4000 — — ns Output valid from clock TAA — — 3500 ns Bus free time TBUF 4700 — — ns Note 2 Input filter spike suppression TSP — — 50 ns SDA and SCL pins (Note 1) I2C Fast Mode Clock frequency FSCL 0— 400 kHz Clock high time THIGH 600 — — ns Clock low time TLOW 1300 — — ns SDA and SCL rise time TR 20 + 0.1CB — 300 ns From VIL to VIH (Note 1) SDA and SCL fall time TF 20 + 0.1CB — 300 ns From VIL to VIH (Note 1) START condition hold time THD:STA 600 — — ns START condition setup time TSU:STA 600 — — ns Data input hold time THD:DAT 0— 0.9 ms Data input setup time TSU:DAT 100 — — ns STOP condition setup time TSU:STO 600 — — ns STOP condition hold time THD:STD 600 — — ns Output valid from clock TAA —— 900 ns Bus free time TBUF 1300 — — ns Note 2 Input filter spike suppression TSP — — 50 ns SDA and SCL pins (Note 1) Note 1: This parameter is periodically sampled and not 100% tested. 2: Time the bus must be free before a new transmission can start. TF THIGH VHYS TR TSU:STA TSP THD:STA TLOW THD:DAT TSU:DAT TSU:STO TBUF TAA SCL SDA IN SDA OUT |
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