AD7768BSTZ datasheet(96/106 Pages) AD

96 / 106 page

Data Sheet

AD7768/AD7768-4

AD7768-4 REGISTER MAP DETAILS (SPI CONTROL)

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Rev. C | 96 of 106

Table 66. Bit Descriptions for Channel Mode B

Bits

Bit Name

Settings

Description

Reset

Access

101 ×1024

110 ×1024

111 ×1024

CHANNEL MODE SELECT REGISTER

Address: 0x03, Reset: 0x00, Name: Channel Mode Select

This register selects the mapping of each ADC channel to either Channel Mode A or Channel Mode B.

Table 67. Bit Descriptions for Channel Mode Select

Bits

Bit Name

Settings

Description

Reset

Access

CH_3_MODE

Channel 3.

0x0

0 Mode A.

1 Mode B.

CH_2_MODE

Channel 2.

0x0

0 Mode A.

1 Mode B.

CH_3_MDE_EN

Channel 3 Mode Enable. This bit must be same as CH_3_MODE bit.

0x0

0 Mode A.

1 Mode B.

CH_2_MDE_EN

Channel 2 Mode Enable. This bit must be same as CH_2_MODE bit.

0x0

0 Mode A.

1 Mode B.

CH_1_MODE

Channel 1.

0x0

0 Mode A.

1 Mode B.

CH_0_MODE

Channel 0.

0x0

0 Mode A.

1 Mode B.

POWER MODE SELECT REGISTER

Address: 0x04, Reset: 0x00, Name: POWER_MODE

Table 68. Bit Descriptions for POWER_MODE

Bits

Bit Name

Settings

Description

Reset

Access

SLEEP_MODE

In sleep mode, many of the digital clocks are disabled and all of the ADCs are disabled. The analog

LDOs are not disabled.

0x0

The AD7768-4 SPI is live and is available to the user. Writing to this bit brings the AD7768-4 out of

sleep mode again.

0 Normal operation.

1 Sleep mode.

[5:4]

POWER_MODE

Power Mode. The power mode bits control the power mode setting for the bias currents used on all

ADCs on the AD7768-4. The user can select the current consumption target to meet the application.

The power modes of fast, median, and low power give optimum performance when mapped to the

correct MCLK division setting. These power mode bits do not control the MCLK division of the ADCs.

See the MCLK_DIV bits for control of the division of the MCLK input.

0x0

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