 2004 Microchip Technology Inc.

DS21125E-page 3

24FC65

TABLE 1-3:

AC CHARACTERISTICS

FIGURE 1-2:

BUS TIMING DATA

Parameter

Symbol

1 MHz Bus

Units

Remarks

Min

Max

Clock frequency

0

1000

kHz

Clock high time

THIGH

500

—

ns

Clock low time

500

—

ns

SDA and SCL rise time

—

300

ns

(Note 1)

SDA and SCL fall time

—

100

ns

(Note 1)

START hold time

250

—

ns

After this period the first clock pulse is

generated

START setup time

250

—

ns

Only relevant for repeated START

Data input hold time

0—

ns

Data input setup time

100

—

ns

STOP setup time

250

—

ns

Output valid from clock

—

350

ns

(Note 2)

Bus free time

500

—

ns

Time the bus must be free before a

new transmission can start

Write cycle time

—

5

ms/page (Note 3)

Endurance

High Endurance Block

Rest of Array

10M

1M

—

—

cycles

25°C, Vcc = 5.0V, Block Mode

(Note 4)

Note 1: Not 100 percent tested.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 100 ns) of the falling edge of SCL to avoid unintended generation of START or STOPs.

3: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write

cache for total time.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our website.

SCL

SDA

IN

SDA

OUT