24LCS21 datasheet(11/24 Pages) MICROCHIP

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DS21127F-page 11

24LCS21

6.0

WRITE PROTECTION

When using the 24LCS21 in the Bidirectional mode, the

VCLK pin operates as the write-protect control pin. Set-

ting VCLK high allows normal write operations, while

setting VCLK low prevents writing to any location in the

array. Connecting the VCLK pin to VSS would allow the

24LCS21 to operate as a serial ROM, although this

configuration would prevent using the device in the

Transmit-Only mode.

Additionally, pin 3 performs a flexible write-protect

function. The 24LCS21 contains a write protection

control fuse whose factory default state is cleared.

Writing any data to address 7Fh (normally the

checksum in DDC applications) sets the fuse which

enables the WP pin. Until this fuse is set, the 24LCS21

is always write enabled (if VCLK = 1). After the fuse is

set, the write capability of the 24LCS21 is determined

by WP (Figure 6-1).

TABLE 6-1:

WRITE-PROTECT TRUTH

TABLE

7.0

READ OPERATION

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

slave address is set to one. There are three basic types

of read operations: current address read, random read

and sequential read.

7.1

Current Address Read

The 24LCS21 contains an address counter that

maintains the address of the last word accessed,

internally incremented by one. Therefore, if the

previous access (either a read or write operation) was

to address n, the next current address read operation

would access data from address n + 1. Upon receipt of

the slave address with R/W bit set to one, the 24LCS21

issues an acknowledge and transmits the eight-bit data

word. The master will not acknowledge the transfer, but

does generate a Stop condition and the 24LCS21

discontinues transmission (Figure 7-1).

FIGURE 7-1:

CURRENT ADDRESS

READ

7.2

Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, first the word address must

be set. This is done by sending the word address to the

24LCS21 as part of a write operation. After the word

address is sent, the master generates a Start condition

following the acknowledge. This terminates the write

operation, but not before the internal Address Pointer is

set. Then the master issues the control byte again but

with the R/W bit set to a one. The 24LCS21 will then

issue an acknowledge and transmits the eight-bit data

word. The master will not acknowledge the transfer, but

does generate a Stop condition and the 24LCS21

discontinues transmission (Figure 7-2).

VCLK

Add. 7Fh

Written

Mode

0XX

Read-only

R/W

/open

Yes

R/W

Yes

Read-only

Control

Byte

Data n

Bus Activity

SDA Line

Bus Activity

Master

101 0000 1

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