1999 Dec 14

13

Philips Semiconductors

Product specification

QPSK transmitter

TDA8050

APPLICATION INFORMATION

Table 1

Data format; note 1

Notes

1. X = don’t care.

2. MP1 and MP0: modulator reference divider ratio (see Table 2).

3. When OEN (output enable) is at logic 0, output is disabled, at logic 1 output is enabled.

4. CR2 to CR0: converter synthesizer charge pump current (see Table 3).

5. When DAC4 to DAC0 is at logic 0 minimum gain is programmed, at logic 1 maximum gain is programmed.

DATA

ADDRESS

D11

first in

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

AD1

AD0

last in

Modulator reference divider

ratio

Converter reference divider ratio

X

X

R7

R6

R5

R4

R3

R2

R1

R0

0

1

Control register

X

X

X

CR1

DAC3

DAC2

DAC1

DAC0

1

0

Main divider ratio

P11

P10

P9

P8

P7

P6

P5

P4

P3

P2

P1

P0

1

1

handbook, full pagewidth

MBL113

CLK

DATA

EN

td(strt)

td(stp)

th(CLK)

tsu

Tcy

Fig.8 3-wire bus timing.