MPM54313 datasheet(43/49 Pages) MPS

43 / 49 page

MPM54313

– 16V, TRIPLE 3A POWER MODULE WITH I2C

MPM54313 Rev. 1.0

MonolithicPower.com

5/7/2024

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

The output voltage ripple can be calculated with

Equation (7):

OUT

ESR

8 f





 −







 

(7)

Where L1 is the inductance and RESR is the output

capacitor’s equivalent series resistance (ESR).

For

ceramic

capacitors,

the

capacitance

dominates the impedance at the switching

frequency and causes the majority of the output

voltage ripple. For simplification, the output

voltage ripple can be estimated with Equation (8):

OUT

ΔV1

8 f



 −





 



(8)

For tantalum or electrolytic capacitors, the ESR

dominates the impedance at the switching

frequency. For simplification, the output ripple

can be calculated with Equation (9):

OUT

ESR

ΔV



 −









(9)

The characteristics of the output capacitor also

affect the stability of the regulation.

PCB Layout Guidelines

For the best results, refer to Figure 12 and follow

the guidelines below:

1. Keep the power loop as small as possible.

2. Use a large ground plane to connect directly

to PGND.

3. Place a sufficient ceramic input capacitor as

close to the device as possible.

4. Place the VCC capacitor as close to the VCC

and GND pins as possible.

5. Connect VIN, VOUT, and GND to a large

copper area to improve thermal performance

and long-term reliability.

6. Separate the input GND area from other

GND areas on the top layer.

7. Connect the GND areas together on the

internal layers and connect the bottom layer

through multiple vias to minimize noise.

VIN

VOA

VOB

VOC

GND

Figure 12: Recommended PCB Layout

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