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M45PE10 bảng dữ liệu(PDF) 13 Page - STMicroelectronics

tên linh kiện M45PE10
Giải thích chi tiết về linh kiện  1 Mbit, low voltage, Page-Erasable Serial Flash memory with byte-alterability and a 50 MHz SPI bus interface
PDF  45 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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M45PE10 bảng dữ liệu(HTML) 13 Page - STMicroelectronics

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M45PE10
Operating features
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4.3
A fast way to modify data
The Page Program (PP) instruction provides a fast way of modifying data (up to 256
contiguous bytes at a time), provided that it only involves resetting bits to 0 that had
previously been set to 1.
This might be:
when the designer is programming the device for the first time
when the designer knows that the page has already been erased by an earlier Page
Erase (PE) or Sector Erase (SE) instruction. This is useful, for example, when storing a
fast stream of data, having first performed the erase cycle when time was available
when the designer knows that the only changes involve resetting bits to 0 that are still
set to 1. When this method is possible, it has the additional advantage of minimizing the
number of unnecessary erase operations, and the extra stress incurred by each page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted Bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few Bytes (see Page Program (PP)
and AC characteristics (50 MHz operation)).
4.4
Polling during a Write, Program or Erase cycle
A further improvement in the write, program or erase time can be achieved by not waiting for
the worst case delay (tPW, tPP, tPE, or tSE). The Write In Progress (WIP) bit is provided in the
Status Register so that the application program can monitor its value, polling it to establish
when the previous cycle is complete.
4.5
Reset
An internal Power On Reset circuit helps protect against inadvertent data writes. Addition
protection is provided by driving Reset (Reset) Low during the Power-on process, and only
driving it High when VCC has reached the correct voltage level, VCC(min).
4.6
Active Power, Standby Power and Deep Power-Down modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the Active Power
mode until all internal cycles have completed (Program, Erase, Write). The device then goes
in to the Standby Power mode. The device consumption drops to ICC1.
The Deep Power-down mode is entered when the specific instruction (the Deep Power-
down (DP) instruction) is executed. The device consumption drops further to ICC2. The
device remains in this mode until another specific instruction (the Release from Deep
Power-down and Read Electronic Signature (RES) instruction) is executed.
All other instructions are ignored while the device is in the Deep Power-down mode. This
can be used as an extra software protection mechanism, when the device is not in active
use, to protect the device from inadvertent Write, Program or Erase instructions.



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