LD9535GS datasheet(11/16 Pages) LEADTREND

11 / 16 page

LD9535

01/08/2019

Leadtrend Technology Corporation

www.leadtrend.com.tw

LD9535-DS-00 January 2019

VCC

GND

LD9535

Drain

LEB time

VBULK

)

(







Inductance of primary winding



Resonance equivalent parasitic capacitance

If VDS voltage falls to resonant valley level from max

plateau value, the QRD comparator will be tripped while

FB pin current is close to 20

A.

However, the QR detection will be influenced by

propagation delay. If inductance of primary winding is

less than 500µH, there is barb in Vds (as shown in Fig.

13).

L<500μH

Vaux

VQRD(IFB=20µA)

TPD

Fig. 13

Voltage Feedback Loop

The voltage feedback signal is provided from the TL431

at the secondary side through the photo-coupler to the

COMP pin of the LD9535. Similar to UC3842, the

LD9535 would without voltage offset to feed the voltage

divider at the ratio of RA and RB, that is,

COMP

)

PWM

(

COMPARATOR









A pull-high resistor is embedded internally and therefore

no external one is required.

The LD9535 integrates the multi-mode PWM controller,

and for enhance the light load efficiency, the comp pin

value corresponding to the frequency is as shown in Fig.

14.

VCOMP

FSW

65kHz

24kHz

0.5V 0.6V

Green Mode + QR PWM/CCM

1.1V

1.3V

Max. frequency depends on LM

Fig. 14

Current Sensing, Leading Edge Blanking

The typical current mode of PWM controller feedbacks

both current signal and voltage signal to close the

control loop and achieve regulation. The LD9535 detect

the primary MOSFET current from the CS pin, which is

not only for the peak current mode control but also for

the pulse-by-pulse current limit. The maximum voltage

threshold of the current sensing pin sets at 0.5V. From

above, the MOSFET peak current can be obtained from

below.

)

MAX

(

PEAK



A leading-edge blanking (LEB) timer is included in the

input of CS pin to prevent false trigger from the turn-on

current spike (as shown in Fig. 15).

Fig. 15

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