LD7592SGS datasheet(11/16 Pages) LEADTREND

11 / 16 page

LD7592S

05/08/2018

Leadtrend Technology Corporation

www.leadtrend.com.tw

LD7592S-DS-00 May 2018

ramp is determined by an external resistor connected to

the RAMP pin. The voltage of the RAMP pin is 2.9V and

the slope is proportional to the current flowing out of the

RAMP pin. The internal ramp signal has a 1V offset;

therefore, the drive output will be shut down if the voltage

of the COMP pin is lower than 0.95V. The programmed

on-time will be at its maximum when the COMP pin pulls

high. The COMP pin open voltage is about VCompclamp.

According to the slope of the internal ramp, the maximum

on-time can be programmed. The necessary maximum

on-time will be achieved depending on the boost inductor,

lowest AC line voltage, and maximum output power. The

resistor

value

should

designed

properly.

The

maximum on-time can be obtained from below

6875

RAMP

)

MAX

(

Time







(Sec.)

RRAMP

1V Offest

Turn-off

Signal

Saw

Tooth

Greneator

Comp

2.9V

RAMP

Fig. 13

Output Drive Stage

An output stage of a CMOS buffer, with typical

900mA/-1200mA driving capability, is incorporated to

drive a power MOSFET directly.

The output voltage is

clamped at 13V to protect the MOSFET gate even when

the VCC voltage is higher than 13V.

Current

Sensing

and

Leading-Edge

Blanking

The typical voltage mode of PFC controller feedbacks the

voltage signals to close the control loop and achieve

regulation. The LD7592S detects the inductor current

from the CS pin, which is for the pulse-by-pulse current

limit. The maximum current threshold of the current

sensing pin is set at 200

μA. From above, the inductor

peak current can be obtained from below.

SNS

)

MAX

(

PEAK

200







(A)

A 350ns leading-edge blanking (LEB) time is included in

the input of CS pin to prevent the false-trigger from the

current spike.

Zero Current Detection

In DCM operation, the inductor current decreases during

MOSFET off. The current, ISNS, sourced from CS pin

also decreases simultaneously. When ISNS becomes

smaller than IZCD, MOSFET will be turned on again. Since

the voltage of CS pin is clamped at 0V, ISNS can be shown

below, as shown in Fig. 14 and Fig. 15.

SNS

CSA

SNS



(A)

Because of the inrush current of the boost topology,

VCSA will be a large negative voltage at startup.

Meanwhile, LD7592S may be not enabled so the

clamping circuit of CS pin does not work. ISNS flowing

through the ESD diode of CS pin can only be limited by

RSNS. To prevent too large ISNS from damaging

LD7592S, the resistance value of RSNS is recommended

to be larger than 1kΩ.

ISNS

RCS

RSNS

ZCD

Comparator

μA

ZCD

VCSA

Fig. 14

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