6

AMI Semiconductor

- Preliminary

www.amis.com

XPressArray-II 0.15m

mm Structured ASIC

Data Sheet

Figure 5: Digital Controlled Impedence Termination Modes

The XPressArray-II architecture supports abundant embedded

block RAM as well as distributed RAM constructed from the

structured ASIC logic fabric.

The XPressArray-II 18K embedded dual-port memory block

provides drop-in replacement features for FPGA memories.

Each memory is individually port configurable as 512x36,

1024x18, 2048x9, 4096x4, 8192x2, and 16384x1 as shown in

Table 4. This fully synchronous memory supports read before

write, write before read and write without read operational

modes.

XPressArray-II embedded RAM blocks may be

configured as single-port (1RW), 2-port (1R1W) or true dual-

port (2RW). Each RAM bit is initializable by a late metal mask

option.

The XPressArray-II logic fabric is specifically designed to

support distributed memories to replace FPGA memories

created from LUTs. Pre-designed distributed memories are

available in a range of sizes from 16x1 through 32x32 in 2-port

(1R1W) configurations as shown in Table 5. Additional sizes

and configurations, such as 2-read, 1-write (2R1W)

configurations can also be constructed. Fully synchronous

and synchronous-write, asynchronous read modes are

available. Like the block RAM, each bit is initializable by a late

metal mask option.

6.0 Memory Description

R=Z

R=Z

0

R=Z

0

R=Z

0

R=2Z

0

R=2Z

0

VCC

VCC

VCC/2

VCC

R=Z

Series

Termination

Parallel

Termination

Split

Parallel

R=2Z

0

External

Termination

Internal

Termination

R=Z

R=Z

0

R=Z

0

R=Z

0

R=2Z

0

R=2Z

0

VCC

VCC

VCC/2

VCC

R=Z

Series

Termination

Parallel

Termination

Split

Parallel

R=2Z

0

External

Termination

Internal

Termination