Figure 45. Hot-swap management with DE rising high before and after VCC

Electrostatic discharge (ESD) protection

The ST4E1216 and ST4E1240 have internal protection against electrostatic discharge (ESD).

At circuit level, the ST4E1216 and ST4E1240 they comply with the human body model (ANSI/ESDA/JEDEC

JS-001) to guarantee robustness during the manufacturing process. All the pins of the ST4E1216 and ST4E1240

sustain 2 kV.

Because these transceivers are part of a system and can be connected to its outside through the bus terminals A

and B, an ESD protection is implemented on A and B to comply with IEC 61000-4-2 standard.

The schematic below compares the simplified pulse generator between the circuit-level ESD pulse and the

system-level ESD pulse.

Figure 46. HBM JEDEC (left) and IEC61000-4-2 (right) generator simplified schematics

For an equivalent ESD pulse voltage, the peak current and rise time of the pulse is much higher for the

IEC61000-4-2 than for the HBM. This can be shown by the pulse’s diagrams below, for 8 kV and 12 kV

respectively.

ST4E1216, ST4E1240

Detailed description

DS14542 - Rev 2

page 22/31