AMIS-710200:200dpi CIS Module

Data Sheet

Table 6: Symbol Definitions for the Above Timing Diagram

Item

Symbol

Min.

Mean

Max.

Units

Clock cycle time

to

0.20

2.0

µs

Clock pulse width

tw

50

ns

Clock duty cycle

25

75

%

Prohibit crossing time of SP

tprh

15

ns

Data setup time

tds

10

ns

Data hold time

tdh

35

ns

Signal delay time

tdl

20

ns

Signal settling time

tsh

90

ns

9.0 Mechanical Description

Figure 4 is an overview drawing of the module with approximate dimensions. If a detailed drawing is desired, especially for a design in

application, a full size drawing is available upon request.

Figure 4: AMIS-710200 Module Outline

6

AMI Semiconductor – May 06, M-8-001

www.amis.com