LTC1264CSW datasheet(5/16 Pages) LINER

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LTC1264

1264fb

V +, V – (Pins 7, 19): Power Supply Pins. The V+ (Pin 7) and

the V – (Pin 19) should each be bypassed with a 0.1

µF

capacitor to an adequate analog ground. The filter’s power

supplies should be isolated from other digital or high

voltage analog supplies. A low noise linear supply is

recommended. Using a switching power supply will lower

the signal-to-noise ratio of the filter. The supply during

power-up should have a slew rate less than 1V/

µs. When

V + is applied before V – and V – is allowed to go above

ground, a diode should clamp V – to prevent latch-up.

Figures 1 and 2 show typical connections for dual and

single supply operation.

AGND (Pin 6): Analog Ground Pin. The filter performance

depends on the quality of the analog signal ground. For

either dual or single supply operation, an analog ground

plane surrounding the package is recommended. The

analog ground plane should be connected to any digital

ground at a single point. For dual supply operation, Pin 6

should be connected to the analog ground plane. For

single supply operation, Pin 6 should be biased at 1/2

supply and should be bypassed to the analog ground plane

with at least a 1

µF capacitor (Figure 2). For single 5V

operation and fCLK greater than 1MHz, pin 6 should be

biased at 2V. This minimizes passband gain and phase

variations.

Figure 2. Single Supply Ground Plane Connections

Figure 1. Dual Supply Ground Plane Connections

µF

1264 F02

200

Ω

V+

LTC1264

CLOCK

SOURCE

ANALOG

GROUND

PLANE

DIGITAL

GROUND

PLANE

V+/2

V+

* FOR MODE 3, THE S NODE PINS 5, 8,

17, 20 SHOULD BE TIED TO PIN 6

STAR

SYSTEM

GROUND

0.1

µF

–7.5V

1264 F01

200

Ω

7.5V

LTC1264

CLOCK

SOURCE

0.1

µF

ANALOG

GROUND

PLANE

STAR

SYSTEM

GROUND

DIGITAL

GROUND

PLANE

* OPTIONAL, 1N4148, 1N5819

PI FU CTIO S

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