SST31LF021 datasheet(7/24 Pages) SST

7 / 24 page

EOL Data Sheet

2 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF021 / SST31LF021E

S71137-06-EOL

05/07

TABLE

2: PIN DESCRIPTION

Symbol

Pin Name

Functions

AMS1-A0

Address Inputs

To provide memory addresses.

During flash Sector-Erase, A17-A12 address lines will select the sector.

A17-A0 to provide flash address

A16-A0 to provide SST31LF021/021E SRAM

addresses

DQ7-DQ0

Data Input/Output

To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a flash Erase/Program cycle.

The outputs are in tri-state when OE# or BES# and BEF# are high.

BES#

SRAM Memory Bank Enable

To activate the SRAM memory bank when BES# is low.

BEF#

Flash Memory Bank Enable

To activate the Flash memory bank when BEF# is low.

OE#

Output Enable

To gate the data output buffers.

WE#

Write Enable

To control the Write operations.

VDD

Power Supply

3.0-3.6V Power Supply

VSS

Ground

T2.3 1137

1. AMS = Most significant address

TABLE

3: OPERATION MODES SELECTION

Mode

BES#

BEF#

OE#

WE#

Address

Flash

Read

1. X can be VIL or VIH, but no other value.

VIL

VIH

AIN

DOUT

AIN

Program

VIL

VIH

VIL

AIN

DIN

AIN

Erase

VIL

VIH

VIL

Sector address,

XXH for Bank-Erase

SRAM

Read

VIL

VIH

VIL

VIH

AIN

DOUT

AIN

Write

VIL

VIH

XVIL

AIN

DIN

AIN

Standby

VIHC

High Z

Flash Write Inhibit

VIL

High Z / DOUT

VIH

High Z / DOUT

XVIH

High Z / DOUT

Product Identification

Hardware Mode

VIL

VIH

Manufacturer’s ID (BFH)

Device ID2

2. Device ID 18H for SST31LF021, 19H for SST31LF021E.

A17-A1=VIL, A0=VIL

A17-A1=VIL, A0=VIH

Software Mode

VIL

VIH

AIN

ID Code

See Table 4

T3.4 1137

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