S71PL129JC0 datasheet(134/153 Pages) SPANSION

tên linh kiện	S71PL129JC0

Giải thích chi tiết về linh kiện	Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM 128 Megabit (8M x 16-bit) CMOS3.0 Volt-only Simultaneous Operation, Page Mode Flash Memory

PDF	153 Pages

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nhà sản xuất	SPANSION [SPANSION]

Trang chủ	http://www.spansion.com

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This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not

design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.

Publication Number S71PL129Jxx_00

Revision A Amendment 8 Issue Date October 28, 2005

Features

Asynchronous SRAM Interface

Fast Access Time

—tCE = tAA = 60 ns max (16M)

—tCE = tAA = 65 ns max (32M/64M)

8 words Page Access Capability

—tPAA = 20 ns max (32M/64M)

Low Voltage Operating Condition

—VDD = +2.7 V to +3.1 V

Wide Operating Temperature

— TA = -30°C to +85°C

Byte Control by LB and UB

Various Power Down modes

— Sleep (16M)

— Sleep, 4M-bit Partial, or 8M-bit Partial (32M)

— Sleep, 8M-bit Partial, or 16M-bit Partial (64M)

Pin Description

pSRAM Type 7

16Mb(1M word x 16-bit)

32Mb(2M word x 16-bit)

64Mb(4M word x 16-bit)

CMOS 1M/2M/4M-Word x 16-bit pSRAM

ADVANCE

INFORMATION

Pin Name

Description

A21 to A0

Address Input: A19 to A0 for 16M, A20 to A0 for 32M, A21 to A0 for 64M

CE1#

Chip Enable (Low Active)

CE2

Chip Enable (High Active)

WE#

Write Enable (Low Active)

OE#

Output Enable (Low Active)

UB#

Upper Byte Control (Low Active)

LB#

Lower Byte Control (Low Active)

DQ16-9

Upper Byte Data Input/Output

DQ8-1

Lower Byte Data Input/Output

VDD

Power Supply

VSS

Ground

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