SAF7113 datasheet(52/80 Pages) PHILIPS

52 / 80 page

2000 May 08

Philips Semiconductors

Product speciﬁcation

9-bit video input processor

SAF7113H

15.2

I2C-bus detail

The I2C-bus receiver slave address is 48H/49H.

Subaddresses 14H, 18H to 1EH, 20H to 3FH and

63H to FFH are reserved.

15.2.1

SUBADDRESS 00H (READ ONLY REGISTER)

Table 25 Chip version SA 00

15.2.2

SUBADDRESS 01H

Table 26 Horizontal increment delay

The programming of the horizontal increment delay is

used to match internal processing delays to the delay of

the ADC. Use recommended position only.

FUNCTION

LOGIC LEVELS

ID07

ID06

ID05

ID04

Chip Version (CV)

CV3

CV2

CV1

CV0

FUNCTION

IDEL3 IDEL2 IDEL1 IDEL0

No update

1111

Minimum delay

1110

Recommended

position

1000

Maximum delay

0000

15.2.3

SUBADDRESS 02H

Table 27 Analog control 1 SA 02

Notes

1. Mode select (see Figs 35 to 42).

2. To take full advantage of the YC-modes 6 to 9 the I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1

(full luminance bandwidth).

FUNCTION(1)

CONTROL BITS D3 TO D0

MODE 3 MODE 2 MODE 1 MODE 0

Mode 0: CVBS (automatic gain) from AI11 (pin 4)

0000

Mode 1: CVBS (automatic gain) from AI12 (pin 7)

0001

Mode 2: CVBS (automatic gain) from AI21 (pin 43)

0010

Mode 3: CVBS (automatic gain) from AI22 (pin 1)

0011

Mode 4: reserved

0100

Mode 5: reserved

0101

Mode 6: Y (automatic gain) from AI11 (pin 4) + C (gain adjustable via

GAI28 to GAI20) from AI21 (pin 43); note 2

0110

Mode 7: Y (automatic gain) from AI12 (pin 7) + C (gain adjustable via

GAI28 to GAI20) from AI22 (pin 1); note 2

0111

Mode 8: Y (automatic gain) from AI11 (pin 4) + C (gain adapted to Y gain)

from AI21 (pin 43); note 2

1000

Mode 9: Y (automatic gain) from AI12 (pin 7) + C (gain adapted to Y gain)

from AI22 (pin 1); note 2

1001

Modes 10 to 15: reserved

1111

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